{
  "listing": {
    "skills": [
      {
        "path": "skills/brainstorm/SKILL.md",
        "name": "brainstorm",
        "description": "Use when brainstorming a new module's requirements and architecture into a brainstorm.md, one way to write the intent document the pipeline starts from; not for design.md, RTL, constraints, or any in-pipeline stage.",
        "files": {
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      },
      {
        "path": "skills/design-flow/SKILL.md",
        "name": "design-flow",
        "description": "Use when progressing IC design through stages, checking module status, or routing rework decisions; not for single-stage execution or artifact authoring.",
        "files": {
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      },
      {
        "path": "skills/env-precheck/SKILL.md",
        "name": "env-precheck",
        "description": "Use when checking whether this machine's Python, EDA tools and licenses can actually run VeriPower's stages; not for any pipeline stage, module state, or design work.",
        "files": {
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        "name": "lint-cdc",
        "description": "Check RTL lint and clock-domain crossings with SpyGlass, evaluate violations and justified waivers, and close the current assessment.",
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        "description": "Build and check power experiments, calculate averaged gate-level power with SAIF and PT-PX, and assess the results against the task's power requirements; not for functional regression or static timing analysis.",
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        "description": "Use when writing or modifying RTL and its file/constraint annotations, reviewing implementation against requirements, or repairing an implementation defect; not for running synthesis or functional regression as a pipeline stage.",
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      },
      {
        "path": "skills/simulation/SKILL.md",
        "name": "simulation",
        "description": "Implement, review and run a module's functional testbench, diagnose verification failures and assess coverage; not for changing upstream RTL or requirements.",
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        "name": "simulation-triage",
        "description": "Diagnose a failed verification run from requirements, implementation and experimental evidence, and identify the repair owner; not for editing canonical design or verification artifacts.",
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        "description": "Establish requirements, design decisions, interfaces, clocks and constraints from the delivered intent, or revise them after evidence-based clarification; not for implementing RTL or verification.",
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